Non-volatile memory technology is marked by continued efforts to produce smaller memory cells and higher capacity memory devices. Conventionally, much of the development has been focused on developing floating gate flash memory devices, but the drive to develop even smaller memory cells is somewhat hindered by floating gate structures. For example, as the size of the tunnel oxide film present in floating gate memory structures is further reduced, the structure becomes more susceptible to leakage current, which will result in the loss of charges in the floating gate.
In an effort to overcome the limitations imposed by floating gate flash memory structures in further reducing the size of memory cells, flash memories utilizing oxide nitride oxide (ONO) films, such as, for example, in metal oxide nitride oxide silicon (MONOS) and silicon oxide nitride oxide silicon (SONOS) structures, have been developed. Charges accumulate in the silicon nitride film layer, otherwise known as the trap layer, of the ONO film. The use of the ONO film helps to alleviate the possibility of charge loss in the tunnel oxide layer.
FIG. 1 illustrates a conventional memory structure having an ONO film. The SONOS structure 1 of FIG. 1 having a substrate 10 and an ONO film 20 disposed thereupon. The ONO film 20 comprises a silicon nitride layer 40 surrounded by a lower oxide layer 30 and an upper oxide layer 50. A conductive layer 60 representative of a control gate structure is disposed on the ONO film 20. A hard mask (HM) layer 70 may be deposited over the conductive layer 60.
In operation, the SONOS structure 1 may be part of a channel 80 in the substrate 10 having a source side 90 and a drain side 100. Electrons in the channel 80 may gain enough energy to overcome the dielectric barrier imposed by the lower oxide layer 30 and become trapped in the silicon nitride layer 40. The silicon nitride layer 40, itself being non-conductive, is capable of holding a source side charge 110 that will not migrate through the layer proximate to the source side 90 and a drain side charge 120 that will not migrate through the layer proximate to the drain side 100. Therefore, the SONOS structure 1 having the characteristic that it is capable of holding two bits of information.
The presence or absence of a charge in the source side charge 110 and the drain side charge 120 is determined by sensing the change in their threshold voltages upon application of a read voltage. If either the source side charge 110 or the drain side charge 120 does indeed hold a charge, then the threshold voltage will increase upon application of the read voltage. However, the source side charge 110 and drain side charge 120 may interact depending upon the extent of threshold voltage experienced during a read operation. Any resulting interaction is known as a second bit effect.
For example, if both the source side charge 110 and the drain side charge 120 have low threshold voltages, then any interaction between the source side charge 110 and the drain side charge 120 may be avoided by simply selecting a lower read voltage. However, if, for example, the drain side charge 120 has a high threshold voltage and the source side charge 110 has a low threshold voltage, then as the threshold voltage of the drain side charge 120 further increases upon application of the read voltage, the higher threshold voltage of the drain side charge 120 may cause the source side charge 110 to also be incorrectly read as possessing a charge.
While this second bit effect has conventionally been overcome by increasing the drain voltage and/or decreasing the doping concentration of the substrate, both of these solutions each have their own limitations. Increasing the drain voltage reduces the voltage difference that may be experienced between the source side charge 110 and the drain side charge 120, but as the size of these memory devices becomes further reduced, higher a higher drain voltage increases the potential for current drain leakage.
Low substrate doping concentration may lead to unacceptable punch through behavior, which may result in a reduction in the length of the channel resulting in a short channel effect. The short channel effect may cause the erroneous registering of an off state or an on state in the transistor.
There remains a need in the art for improved ONO memory cell structures that overcomes the second bit effect commonly experienced by such structures.
FIG. 2A illustrates a SONOS structure fabricated according to certain conventional manufacturing techniques. As shown in FIG. 2A a residual layer 130, which is an artifact of an etching process of the conventional manufacturing technique, substantially surrounds the sidewall of the SONOS memory cell. The residual layer 130 may possess conductive properties.
FIG. 2B illustrates a SONOS structure fabricated according to certain conventional manufacturing techniques. As shown in FIG. 2B a particle 140, which more typically remains after an ion implantation process of the conventional manufacturing technique, becomes deposited in a dielectric material surrounding the SONOS memory cell.
FIG. 2C illustrates how current leakage paths may develop in memory devices having a residual layer 130 or a deposited particle 140. While there have been technological improvements to the manufacturing processes for fabricating SONOS memory cells, there remains a need in the art for a SONOS structure whose design discourages the development of current leakage paths.